18 search results - page 4 / 4 » Reducing Communication Latency with Path Multiplexing in Opt... |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...