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DSD
2008
IEEE
108views Hardware» more  DSD 2008»
13 years 6 months ago
Reducing Leakage through Filter Cache
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
Roberto Giorgi, Paolo Bennati
SAC
2008
ACM
13 years 4 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
CASES
2006
ACM
13 years 10 months ago
Reducing energy of virtual cache synonym lookup using bloom filters
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stua...
CASES
2007
ACM
13 years 8 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
IEEEPACT
2007
IEEE
13 years 11 months ago
L1 Cache Filtering Through Random Selection of Memory References
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
Yoav Etsion, Dror G. Feitelson