27 search results - page 1 / 6 » Reducing Memory and Traffic Requirements for Scalable Direct... |
ICPP
1990
IEEE
13 years 8 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
HIPC
2007
Springer
13 years 11 months ago
2007
Springer
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...
ASPLOS
1991
ACM
13 years 8 months ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...