79 search results - page 3 / 16 » Reducing Power Consumption for High-Associativity Data Cache... |
GLVLSI
1998
IEEE
13 years 10 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
ISMVL
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
CF
2004
ACM
13 years 9 months ago
2004
ACM
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
JEC
2006
13 years 6 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...