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NOCS
2009
IEEE
14 years 3 days ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
ISSS
1999
IEEE
149views Hardware» more  ISSS 1999»
13 years 9 months ago
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Synchronous Dataflow, a subset of dataflow, has proven to be a good match for specifying DSP programs. Because of the limited amount of memory in embedded DSPs, a key problem duri...
Praveen K. Murthy, Shuvra S. Bhattacharyya
SCOPES
2004
Springer
13 years 10 months ago
DSP Code Generation with Optimized Data Word-Length Selection
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...
Daniel Menard, Olivier Sentieys
CDES
2006
106views Hardware» more  CDES 2006»
13 years 6 months ago
Reducing Memory References for FFT Calculation
Fast Fourier Transform (FFT) is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication applications. many of t...
Ayman Elnaggar, Mokhtar Aboelaze
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 4 days ago
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique
—Body sensor networks are emerging as a promising platform for healthcare monitoring. These systems are composed of battery-operated embedded devices which process physiological ...
Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozb...