29 search results - page 1 / 6 » Reducing Register Pressure Through LAER Algorithm |
ACSC
2004
IEEE
13 years 8 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
LCTRTS
2007
Springer
13 years 10 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
IEEEPACT
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
CGO
2009
IEEE
13 years 11 months ago
2009
IEEE
—Register allocation is an important component of every compiler and numerous studies have investigated ways to improve allocation quality or reduce allocation time. However, tec...