29 search results - page 3 / 6 » Reducing Register Pressure Through LAER Algorithm |
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
PLDI
2005
ACM
13 years 11 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
GECCO
2004
Springer
13 years 10 months ago
2004
Springer
This paper describes POPE-GP, a system that makes use of the NSGA-II multiobjective evolutionary algorithm as an alternative, parameter-free technique for eliminating program bloat...
WEA
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...