253 search results - page 2 / 51 » Reducing SoC Simulation and Development Time |
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
ICNC
2009
Springer
13 years 11 months ago
2009
Springer
—With the aim to minimize boarding time and devise procedures for boarding strategies, this paper develop the synthesis of Improved Genetic Algorithms and simulation. This paper ...