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» Reducing bus delay in submicron technology using coding
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DAC
2005
ACM
14 years 6 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim
GLOBECOM
2008
IEEE
14 years 7 days ago
Cooperative MAC for Rate Adaptive Randomized Distributed Space-Time Coding
—In a distributed wireless network, it is possible to employ several relays and mimic a multiple antenna transmission system. In this paper we propose a MAC layer solution that a...
Pei Liu, Yuanpeng Liu, Thanasis Korakis, Anna Scag...
VLSISP
2008
108views more  VLSISP 2008»
13 years 5 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
INFOCOM
2010
IEEE
13 years 4 months ago
Multicast Scheduling with Cooperation and Network Coding in Cognitive Radio Networks
—Cognitive Radio Networks (CRNs) have recently emerged as a promising technology to improve spectrum utilization by allowing secondary users to dynamically access idle primary ch...
Jin Jin, Hong Xu, Baochun Li
SC
2005
ACM
13 years 11 months ago
Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters
Left unchecked, the fundamental drive to increase peak performance using tens of thousands of power hungry components will lead to intolerable operating costs and failure rates. H...
Rong Ge, Xizhou Feng, Kirk W. Cameron