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» Reducing bus delay in submicron technology using coding
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ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
13 years 11 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
FPL
2003
Springer
113views Hardware» more  FPL 2003»
13 years 10 months ago
Data Dependent Circuit Design: A Case Study
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
IMC
2007
ACM
13 years 6 months ago
Compressed network monitoring for ip and all-optical networks
We address the problem of efficient end-to-end network monitoring of path metrics in communication networks. Our goal is to minimize the number of measurements or monitors requir...
Mark Coates, Yvan Pointurier, Michael Rabbat
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
13 years 10 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...