88 search results - page 2 / 18 » Reducing energy and delay using efficient victim caches |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
ISMVL
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
ICS
2010
Tsinghua U.
13 years 7 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...