25 search results - page 1 / 5 » Reducing power consumption of instruction ROMs by exploiting... |
APCCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the sw...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
ISVLSI
2008
IEEE
13 years 12 months ago
2008
IEEE
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
ICCD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...