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» Reducing the Area on a Chip Using a Bank of Evolved Filters
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ICES
2007
Springer
90views Hardware» more  ICES 2007»
13 years 11 months ago
Reducing the Area on a Chip Using a Bank of Evolved Filters
Abstract. An evolutionary algorithm is utilized to find a set of image filters which can be employed in a bank of image filters. This filter bank exhibits at least comparable v...
Zdenek Vasícek, Lukás Sekanina
ERSA
2006
99views Hardware» more  ERSA 2006»
13 years 6 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 1 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 2 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 10 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...