43 search results - page 9 / 9 » Reducing the Energy of Speculative Instruction Schedulers |
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
RTSS
1998
IEEE
13 years 9 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...