221 search results - page 1 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
TC
2008
13 years 4 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
ASAP
2003
IEEE
13 years 10 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
DGCI
2005
Springer
13 years 10 months ago
2005
Springer
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...