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» Reducing the number of lines in reversible circuits
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DAC
2010
ACM
13 years 8 months ago
Reducing the number of lines in reversible circuits
Reversible logic became a promising alternative to traditional circuits because of its applications e.g. in low-power design and quantum computation. As a result, design of revers...
Robert Wille, Mathias Soeken, Rolf Drechsler
ISMVL
2008
IEEE
155views Hardware» more  ISMVL 2008»
13 years 11 months ago
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits
—A quaternary reversible circuit is more compact than the corresponding binary reversible circuit in terms of number of input/output lines required. Decoder, multiplexer, and dem...
Mozammel H. A. Khan
ASPDAC
2008
ACM
106views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order re...
Duo Li, Sheldon X.-D. Tan
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
13 years 10 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
ISMVL
2010
IEEE
195views Hardware» more  ISMVL 2010»
13 years 10 months ago
ESOP-Based Toffoli Network Generation with Transformations
In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work [12] and generates a cascade of inverted-control-Toffoli gates from t...
Yasaman Sanaee, Gerhard W. Dueck