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2005
ACM

Complexity reduction in an nRERL microprocessor

10 years 6 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25µm CMOS technology. Its minimum energy consumption of 4.67µA/MHz was measured at Vdd=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Microprocessors and microcomputers. General Terms Design. Keywords Microprocessor, nMOS Reversible Energy Recovery Logic (nRERL), Clocked Power Generator (CP...
Seokkee Kim, Soo-Ik Chae
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ISLPED
Authors Seokkee Kim, Soo-Ik Chae
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