18 search results - page 3 / 4 » Reducing the number of lines in reversible circuits |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
VLSID
1996
IEEE
13 years 10 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
CPAIOR
2004
Springer
13 years 11 months ago
2004
Springer
We discuss a di cult optimization problem on a chess-board, requiring equal numbers of black and white queens to be placed on the board so that the white queens cannot attack the b...
ISMVL
2005
IEEE
13 years 11 months ago
2005
IEEE
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
ISPASS
2010
IEEE
14 years 19 days ago
2010
IEEE
Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been prop...