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GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
13 years 10 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina
DAC
2007
ACM
14 years 5 months ago
Optimization of Area in Digital FIR Filters using Gate-Level Metrics
In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR f...
Eduardo A. C. da Costa, José C. Monteiro, L...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
13 years 10 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
IJCSS
2007
133views more  IJCSS 2007»
13 years 4 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
CEC
2009
IEEE
13 years 11 months ago
Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming
— Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the...
Zbysek Gajda, Lukás Sekanina