18 search results - page 1 / 4 » Reduction of CMOS Power Consumption and Signal Integrity Iss... |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
GLVLSI
2009
IEEE
14 years 5 days ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...