9 search results - page 1 / 2 » Reduction of Fault Latency in Sequential Circuits by using D... |
DFT
2007
IEEE
13 years 11 months ago
2007
IEEE
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...