7 search results - page 1 / 2 » Redundant-wires-aware ECO timing and mask cost optimization |
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
As wireless LAN devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. The test cost of such devices ...