52 search results - page 11 / 11 » Reexecution-Based Analysis of Logic Programs with Delay Decl... |
VTS
2002
IEEE
13 years 10 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
DAC
2009
ACM
13 years 12 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...