39 search results - page 2 / 8 » Register File Architecture Optimization in a Coarse-Grained ... |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resour...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
ERSA
2004
13 years 7 months ago
2004
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
ERSA
2006
13 years 7 months ago
2006
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...