A High Performance Application Representation for Reconfigurable Systems

Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarchies. Mapping applications to these complex systems requires a representation that allows both hardware and software synthesis. Additionally, this representation must enable optimizations that exploit fine and coarse grained parallelism in order to effectively utilize the performance of the underlying reconfigurable architecture. Our work explores a representation based on the program dependence graph (PDG) incorporated with the static single-assignment (SSA) for synthesis to high performance reconfigurable devices. The PDG effectively describes control dependencies, while SSA yields precise data dependencies. When used together, these two representations provide a powerful, synthesizable form that exploits both fine and coarse grained parallelism. Compared to other commonly used representations for reconfigur...

• Type: Conference
• Year: 2004
• Where: ERSA
• Authors: Wenrui Gong, Gang Wang, Ryan Kastner
• Keywords: Coarse Grained Parallelism, ERSA 2004, ERSA 2007, Reconfigurable Computing Systems, Reconfigurable Logic Arrays