6 search results - page 1 / 2 » Register File Power Reduction Using Bypass Sensitive Compile... |
TCAD
2008
13 years 4 months ago
2008
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
ASAP
2003
IEEE
13 years 9 months ago
2003
IEEE
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
CASES
2001
ACM
13 years 8 months ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
TVLSI
2002
13 years 4 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...