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MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
13 years 8 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
13 years 9 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
MASCOTS
2004
13 years 6 months ago
Design and Implementation of a High Speed Microprocessor Simulator BurstScalar
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...
Takashi Nakada, Hiroshi Nakashima
DAC
2000
ACM
14 years 5 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 8 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr