33 search results - page 1 / 7 » Register placement for high-performance circuits |
DSN
2005
IEEE
13 years 10 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
ASPDAC
2011
ACM
12 years 8 months ago
2011
ACM
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
FCCM
1998
IEEE
13 years 9 months ago
1998
IEEE
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...