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ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
13 years 9 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
CODES
1999
IEEE
13 years 9 months ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 2 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha