29 search results - page 3 / 6 » Regular layout generation of logically optimized datapaths |
ASIAN
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. A coinduction-based technique to generate an optimal monitor from a Linear Temporal Logic (LTL) formula is presented in this paper. Such a monitor receives a sequence of ...
DAC
2012
ACM
11 years 8 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
WSC
2008
13 years 8 months ago
2008
In this paper, an automation concept is proposed to facilitate the simulation model building for port design problem. Currently, this process, which includes drawing the terminal ...
FPGA
2007
ACM
14 years 6 days ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...