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» Reliability challenges for 45nm and beyond
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TC
2011
12 years 11 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
DSN
2009
IEEE
13 years 11 months ago
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
Naga Durga Prasad Avirneni, Viswanathan Subramania...
ISPD
2007
ACM
151views Hardware» more  ISPD 2007»
13 years 6 months ago
Pattern sensitive placement for manufacturability
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
Shiyan Hu, Jiang Hu
QSHINE
2009
IEEE
13 years 11 months ago
Revisiting a QoE Assessment Architecture Six Years Later: Lessons Learned and Remaining Challenges
In 2003, we presented an architecture for a streaming video quality assessment system [1]. Six years later, many of the challenges outlined in that paper remain. This paper revisit...
Amy Csizmar Dalal
IJMMS
2006
82views more  IJMMS 2006»
13 years 4 months ago
Current practice in measuring usability: Challenges to usability studies and research
How to measure usability is an important question in HCI research and user interface evaluation. We review current practice in measuring usability by categorizing and discussing u...
Kasper Hornbæk