8 search results - page 1 / 2 » Reliability-Aware SOC Voltage Islands Partition and Floorpla... |
ISVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...