14 search results - page 3 / 3 » Removing Cycles in Esterel Programs |
TCAD
2010
12 years 12 months ago
2010
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
CN
2010
13 years 3 months ago
2010
Conventional simple p-cycle (Preconfigured Protection Cycle) concept allows fast and capacity-efficient span protection in WDM mesh networks. Unlike simple p-cycle, non-simple p-cy...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ISCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...