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» Reorganizing global schedules for register allocation
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ICS
1999
Tsinghua U.
9 years 11 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith
IEEEPACT
2000
IEEE
9 years 11 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
ASPDAC
2008
ACM
127views Hardware» more  ASPDAC 2008»
9 years 9 months ago
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-S...
CC
2002
Springer
131views System Software» more  CC 2002»
9 years 7 months ago
Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
Andrea G. M. Cilio, Henk Corporaal
DAC
1989
ACM
9 years 11 months ago
Scheduling and Binding Algorithms for High-Level Synthesis
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
Pierre G. Paulin, John P. Knight
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