43 search results - page 3 / 9 » Reporting of standard cell placement results |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
The standard cell placement problem has been extensively studied in the past twenty years. Many approaches were proposed and proven e ective in practice. However, successful place...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...