18 search results - page 3 / 4 » Resilient routing implementation in 2D mesh NoC |
DSD
2009
IEEE
14 years 1 days ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...