3 search results - page 1 / 1 » Reticle Floorplanning with Guaranteed Yield for Multi-Projec... |
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...