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» Retiming for Synchronous Data Flow Graphs
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CODES
1996
IEEE
13 years 9 months ago
Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications
The design of multi-dimensional systems using hardware/software codesign allows a significant improvement in the development cycle. This paper presents a technique that enables a ...
Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mea...
DAC
1997
ACM
13 years 9 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
13 years 9 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
CATA
2007
13 years 6 months ago
Static Scheduling for Synchronous Data Flow Graphs
This paper addresses the issue of determining the iteration bound for a synchronous data flow graph (SDFG) and determining whether or not a SDFG is live based on some calculations...
Samer F. Khasawneh, Michael E. Richter, Timothy W....
FMCAD
2006
Springer
13 years 9 months ago
Liveness and Boundedness of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proven to be suitable for specifying and analyzing streaming applications that run on single- or multi-processor platforms. Streaming appl...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...