18 search results - page 3 / 4 » Reuse-Driven Tiling for Improving Data Locality |
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
CLUSTER
2004
IEEE
13 years 9 months ago
2004
IEEE
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
PDP
2009
IEEE
14 years 4 days ago
2009
IEEE
—Multicore machines are becoming common. There are many languages, language extensions and libraries devoted to improve the programmability and performance of these machines. In ...
ISPDC
2008
IEEE
13 years 11 months ago
2008
IEEE
We present a load-balancing technique that exploits the temporal coherence, among successive computation phases, in mesh-like computations to be mapped on a cluster of processors....
VLDB
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...