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» Reversible logic for supercomputing
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VLSID
2006
IEEE
130views VLSI» more  VLSID 2006»
14 years 5 months ago
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array
In this paper, a new realization for logic functions, namely Reversible Programmable Logic Array (RPLA), has been proposed. The proposed realization has the advantage of regularit...
Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Has...
DATE
2010
IEEE
136views Hardware» more  DATE 2010»
13 years 10 months ago
Reversible logic synthesis through ant colony optimization
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...
Min Li, Yexin Zheng, Michael S. Hsiao, Chao Huang
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
13 years 11 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Fast synthesis of exact minimal reversible circuits using group theory
- We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory p...
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...