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IEEEPACT
2007
IEEE
13 years 11 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ENTCS
2007
114views more  ENTCS 2007»
13 years 4 months ago
Parametric Performance Contracts for Software Components with Concurrent Behaviour
Performance prediction methods for component-based software systems aim at supporting design decisions of software architects during early development stages. With the increased a...
Jens Happe, Heiko Koziolek, Ralf Reussner
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
13 years 11 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 8 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 5 months ago
TurboTag: lookup filtering to reduce coherence directory power
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisa...