13 search results - page 3 / 3 » Robust analytical gate delay modeling for low voltage circui... |
ISVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
SAC
2006
ACM
13 years 10 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
TVLSI
2010
12 years 11 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...