59 search results - page 2 / 12 » Runtime leakage power estimation technique for combinational... |
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
VLSID
2010
IEEE
12 years 11 months ago
2010
IEEE
The continuous increase of leakage power consumption
in deep sub-micro technologies necessitates more aggressive
leakage control. Runtime leakage control (RTLC) is effective,
si...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...