19 search results - page 3 / 4 » SAT and ATPG: Boolean engines for formal hardware verificati... |
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
CAV
2009
Springer
14 years 6 months ago
2009
Springer
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
CAV
2004
Springer
13 years 9 months ago
2004
Springer
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
— All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA in...