41 search results - page 2 / 9 » SOI Digital CMOS VLSI - a Design Perspective |
DAC
1996
ACM
13 years 9 months ago
1996
ACM
Aggressive voltage scaling to 1V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology t...
Lecture Notes
VLSI (Very Large Scale Integration) CMOS (Complementary Metal Oxide Semiconductor) technology is the main driver of our digital revolution. The goals of these lecture are to learn ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...