8 search results - page 1 / 2 » SRAM Read Write Margin Enhancements Using FinFETs |
TVLSI
2010
12 years 11 months ago
2010
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
ISQED
2010
IEEE
13 years 6 months ago
2010
IEEE
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
ISQED
2010
IEEE
13 years 3 months ago
2010
IEEE
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...