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» Sampling-rate-aware noise generation
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DAC
2000
ACM
14 years 5 months ago
High-level simulation of substrate noise generation including power supply noise coupling
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total...
Marc van Heijningen, Mustafa Badaroglu, Sté...
CMMR
2005
Springer
69views Music» more  CMMR 2005»
13 years 10 months ago
Generating and Modifying Melody Using Editable Noise Function
This paper introduces a way to generate or modify a melody using the editable noise function. The band-limited random numbers generated by the noise function are converted to the v...
Yong-Woo Jeon, In-Kwon Lee, Jong-Chul Yoon
ISCAS
2007
IEEE
95views Hardware» more  ISCAS 2007»
13 years 11 months ago
Substrate Noise Reduction Based On Noise Aware Cell Design
— A substrate biasing methodology is introduced based on modifying standard cells by inserting dedicated substrate contacts in those cells behaving as aggressive digital noise ge...
Emre Salman, Eby G. Friedman, Radu M. Secareanu, O...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
13 years 11 months ago
Blue-Noise Sigma-Delta Modulator: Improving Substrate Noise and Nonlinear Amplifier Gain Effects
— This paper presents a method to reduce the effects of substrate noise and nonlinear amplifier gain on sigma-delta (Σ∆) modulators through the use of blue-noise modulation. I...
Eric C. Moule, Zeljko Ignjatovic
ISCAS
2007
IEEE
169views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang