314 search results - page 1 / 63 » Sanity Checks in Formal Verification |
CONCUR
2006
Springer
13 years 8 months ago
2006
Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
ICSE
2009
IEEE-ACM
13 years 2 months ago
2009
IEEE-ACM
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
JSA
2008
13 years 4 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
FMSD
2002
13 years 4 months ago
2002
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...