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CATA
2004
13 years 6 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
13 years 11 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
DATE
2004
IEEE
149views Hardware» more  DATE 2004»
13 years 8 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede
CSREAESA
2006
13 years 6 months ago
Field-programmable Gate Array in Miniature Ion Mobility Spectrometer Sensor System
This paper presents the use of field-programmable gate array (FPGA) in a miniature Ion Mobility Spectrometer (IMS) sensor system. This IMS sensor is for detection of subsurface ga...
Jon Cole, S. M. Loo, Robert Youngberg, Jake Baker,...
BMCBI
2008
118views more  BMCBI 2008»
13 years 5 months ago
DOVIS: an implementation for high-throughput virtual screening using AutoDock
Background: Molecular-docking-based virtual screening is an important tool in drug discovery that is used to significantly reduce the number of possible chemical compounds to be i...
Shuxing Zhang, Kamal Kumar, Xiaohui Jiang, Anders ...