30 search results - page 1 / 6 » Satisfiability-Based Detailed FPGA Routing |
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
FPGA
2011
ACM
12 years 8 months ago
2011
ACM
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch b...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...